1. In order to read multiple bytes of a row at the same time, we make use of ______
a :
Memory extension
b :
Cache
c :
Latch
d :
Shift register
Correct Answer: c [Latch]
2. The difference in the address and data connection between DRAM’s and SDRAM’s is _______
a :
The requirement of more address lines in SDRAM’s
b :
The usage of a buffer in SDRAM’s
c :
The usage of more number of pins in SDRAM’s
d :
None of the mentioned
Correct Answer: b [The usage of a buffer in SDRAM’s]
3. The data is transferred over the RAMBUS as _______
a :
Blocks
b :
Swing voltages
c :
Bits
d :
Packets
Correct Answer: b [Swing voltages]
4. The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______
a :
CMOS
b :
Memory sticks
c :
Blue-ray devices
d :
Flash memory
Correct Answer: d [Flash memory]
5. The drawback of building a large memory with DRAM is ______________
a :
The Slow speed of operation
b :
The large cost factor
c :
The inefficient memory organisation
d :
All of the mentioned
Correct Answer: a [The Slow speed of operation]
6. In a 4K-bit chip organisation has a total of 19 external connections, then it has _______ address if 8 data lines are there.
a :
10
b :
12
c :
9
d :
8
Correct Answer: c [9]
7. The bit used to signify that the cache location is updated is ________
a :
Flag bit
b :
Reference Bit
c :
Update Bit
d :
Dirty Bit
Correct Answer: d [Dirty Bit]
8. The bit used to indicate whether the block was recently used or not is _______
a :
Reference bit
b :
Dirty bit
c :
Control bit
d :
Idol bit
Correct Answer: b [Dirty bit]
9. he number successful accesses to memory stated as a fraction is called as _____
a :
Access rate
b :
Success rate
c :
Hit rate
d :
Miss rate
Correct Answer: c [Hit rate]
10. During a write operation if the required block is not present in the cache then ______ occurs.
a :
Write miss
b :
Write latency
c :
Write hit
d :
Write delay
Correct Answer: a [Write miss]
11. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for ________
a :
Id
b :
Word
c :
Tag
d :
Block
Correct Answer: c [Tag]
12. The chip can be disabled or cut off from an external connection using ______
a :
ACPT
b :
RESET
c :
LOCK
d :
Chip Select
Correct Answer: d [Chip Select]
13. The reason for the cells to lose their state over time is ________
a :
Use of Shift registers
b :
The lower voltage levels
c :
Usage of capacitors to store the charge
d :
None of the mentioned
Correct Answer: c [Usage of capacitors to store the charge]
14. The small extremely fast, RAM’s all called as ________
a :
Heaps
b :
Stacks
c :
Cache
d :
Accumulators
Correct Answer: c [Cache]
15. What does VLIW stands for?
a :
Very Long Instruction Width
b :
Very Large Instruction Word
c :
Very Long Instruction Width
d :
Very Long Instruction Word
Correct Answer: d [Very Long Instruction Word]
16. The VLIW architecture follows _____ approach to achieve parallelism.
a :
SISD
b :
MIMD
c :
MISD
d :
SIMD
Correct Answer: b [MIMD]
17. In IA-32 architecture along with the general flags, which of the following conditional flags are provided?
a :
TF
b :
IOPL
c :
IF
d :
All of the mentioned
Correct Answer: d [All of the mentioned]
18. In CISC architecture most of the complex instructions are stored in _____
a :
CMOS
b :
Register
c :
Transistors
d :
Diodes
Correct Answer: c [Transistors]
19. Both the CISC and RISC architectures have been developed to reduce the ______
a :
Time delay
b :
Semantic gap
c :
Cost
d :
All of the mentioned
Correct Answer: b [Semantic gap]
20. The flash memory modules designed to replace the functioning of a hard disk is ______
a :
RIMM
b :
FIMM
c :
Flash Drives
d :
DIMM
Correct Answer: c [Flash Drives]
21. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one, when _____ occurs.
a :
Delay
b :
Miss
c :
Hit
d :
Delayed Hit
Correct Answer: b [Miss]
22. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in the case of ______
a :
Hit
b :
Miss
c :
Delay
d :
None
Correct Answer: a [Hit]
23. The extra time needed to bring the data into memory in case of a miss is called as __________
a :
Delay
b :
Propagation time
c :
Miss Penalty
d :
None
Correct Answer: c [Miss Penalty]
24. The main memory is structured into modules each with its own address register called ______
a :
ABR
b :
TLB
c :
PC
d :
IR
Correct Answer: a [ABR]
25. In memory interleaving, the lower order bits of the address is used to _____________
a :
Get the data
b :
Get the address of the module
c :
Get the address of the data within the module
d :
None of the mentioned
Correct Answer: b [ Get the address of the module]
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