Digital Electronics MCQ
Digital Electronics MCQ
Total Questions: 55
you'll have 20 second to answer each question.
Quiz Result
Total Questions:
Attempt:
Correct:
Wrong:
Percentage:
Quiz Answers
1. Which of the following options comes under the non – saturated logic family in Digital Electronics?
Emitter – coupled Logic
2. Which of the following digital logic circuits can be used to add more than 1 – bit simultaneously?
Ripple – carry adder
3. Which gates in Digital Circuits are required to convert a NOR-based SR latch to an SR flip-flop?
Two 2 input AND gates
4. When does a negative level triggered flip-flop in Digital Electronics changes its state?
When the clock is negative
5. Which of the following options represent the synchronous control inputs in an S – R flip flop?
S and R
6. What must be used along with synchronous control inputs to trigger a change in the flip flop?
Clock
7. What are the basic gates in MOS logic family?
NAND and NOR
8. What will be the output from a D flip – flop if the clock is low and D = 0?
No change
9. Which of the following majorly determines the number of emitters in a TTL digital circuit?
Fan – in
10. What is a switching function that has more than one output called in Digital Electronics?
Multi-output function
11. What is a Circuit?
Closed-loop through which electrons can pass
12. Which of the following is a type of digital logic circuit?
Both Combinational & Sequential logic circuits
13. When can one logic gate drive many other logic gates in Digital Electronics?
When its output impedance is low and the input impedance is high
14. How must the output of a gate in a TTL digital circuit act when it is HIGH?
Acts as a current source
15. What is the minimum distance required for single error detection according to Hamming’s analysis in Digital Electronics?
2
16. What is the minimum distance required for single error detection according to Hamming’s analysis in Digital Electronics?
Check sum method
17. What will be the output from a D flip-flop if D = 1 and the clock is low?
No change
18. What characteristic will a TTL digital circuit possess due to its multi-emitter transistor?
Low capacitance
19. What input should be given to “S” when SR flip – flop is converted to JK flip – flop?
J.Q'
20. What is the group of 1s in 4 cells of a K – map called?
Quad
21. What is the group of 1s in 2 cells of a K – map called?
Pair
22. What will be the frequency of the output from a JK flip – flop, when J = 1, K = 1, and a clock with pulse waveform is given?
Half the frequency of clock input
23. What gate is placed between clock input and the input of AND gate to convert a positive level triggered flip – flop to a negative level triggered flip – flop?
NOT gate
24. In Digital Circuits, which of the following options represent the synchronous control inputs in a T flip flop?
T
25. Which of the following gives the correct number of multiplexers required to build a 32 x 1 multiplexer?
Two 16 x 1 mux
26. How must the output of a gate is LOW in a TTL circuit?
Acts as a current sink
27. What will a TTL digital circuit possess due to the presence of a multi – emitter transistor?
Smaller area
28. How many errors can the Digital Electronics parity method can find in a single word
Single error
29. Which of these flip – flops cannot be used to construct a serial shift register?
T flip – flop
30. Which of these options represent the other name of Inter – Integrated logic?
Merged Transistor Logic
31. Which of the following options is a Current – Mode logic used in Digital Circuits?
ECL
32. Which of these pins will allow to activate and deactivate a multiplexer?
Enable pin
33. Which of the following options are correct for a 4×1 multiplexer?
It has four 3 – input AND gates
34. A priority encoder has four inputs I0, I1, I2, and I3 where I3 has the highest priority and I0 has the least priority. If I2 = 1, what will be the output?
10
35. Which of the following options represent the correct reduction of XY'Z + X'Y'Z ?
Y'Z
36. What frequency division of the pulsed clock signal can be obtained by connecting 4 flip – flops in cascade?
16
37. Which gate is called the anti – coincidence and coincidence gate respectively?
XOR and XNOR
38. How many AND gates are required to construct a 4 – bit parallel multiplier if four 4 – bit parallel binary adders are given?
Sixteen 2 – input AND gates
39. What must be the input given to “R” when SR flip – flop is converted to JK flip – flop?
K.Q
40. How many cycles of addition and shifting in a 4 – bit multiplier are required to perform multiplication using the shift method?
4
41. How many 4 – bit parallel binary adders will be required to construct a 4 – bit parallel multiplier?
4
42. What kind of operation occurs in a J – K flip flop when both inputs J and K are equal to 1?
Toggle operation
43. Which of the following codes is a sequential code?
8421 code
44. Which of the following options correctly represent the characteristic of Excess – 3 code?
It is a reflexive as well as a sequential code
45. The result “X + XY = X” follows which of these laws?
Absorption law
46. Which of the following points is not correct regarding an Ex – NOR gate in Digital Electronics?
It is a one – bit comparator
47. Which of the following is the full form of CISC?
Complex Instruction Set Computer
48. Which of the architecture is power efficient?
RISC
49. Latch is a device with __________
Two stable state
50. Two stable states of latches are ___________
High output & low output
51. When both inputs of SR latches are high, the latch goes ___________
Metastable
52. When both inputs of SR latches are low, the latch __________
It remains in its previously set or reset state
53. The NAND latch works when both inputs are ___________
1
54. Which of the following expressions is in the product-of-sums form?
(A + B)(C + D)
55. Which of the following expressions is in the sum-of-products form?
A * B + C * D
Quiz Result
ReplyDeletePro
12
Total Questions : 55
Attempt: 55
Correct : 53
Wrong : 2
Percentage : 96.36 %